DFF – Design For Fabrication – How to check a solder mask?

DFF – Design For Fabrication – How to check a solder mask?

In diesem Artikel auf Englisch erklärt Hans Hartmann, Sales Manager DACH von Cadlog GmbH, wie man eine Lötmaske überprüft. Recently I was asked what software tools I recommend for PCB (Printed Circuit Board) solder mask checks. So I wanted to write a small article about "DFF" (Design For Fabrication) checks.

"DFF" shall mean, we want to follow rules to ensure, that the PCB fabricator doesn’t have problems in manufacturing.

"DFM" (Design for Manufacturing) shall mean, we want to follow rules to ensure, that during PCB assembly and test, we don’t have problems in manufacturing.

Is this obvious?

Every PCB-Layout design is made, because we want to manufacture it later on.

Is this still obvious?

We do not want problems during manufacturing, because this will cost money.

I expect everyone agrees to both above statements, nevertheless, I am seeing many PCB-Designers who do not make use of DFF or DFM checking methods. Of course the more experienced a PCB-Designer is, the more he knows what to look for in his own designs. Nevertheless, you have so many rules to follow, it might be wise to consider software assistance. But let us first review the kind of problems I am talking about. Let me make simple, yet striking example – about solder mask (SM).

A solder mask or solder resist is a coating layer on the surfaces of our PCBs. It gives us protection against corrosion, improves dielectric strength. Of course, on top of solder pads, we don’t want a solder resist, so we have there a “SMO” Solder Mask Opening.

A solder mask has to fulfill a couple of design rules as you can see in the following illustration which I found in [1]. In orange color we have the copper and the solder mask is in green.

  • SM must have some "clearance" against solder-pad (eg. 50um)
  • SM over traces must have some minimum cover, otherwise might detach (eg. 100um)
  • Between SMO, you will create "Bridge" which has to have a minimum size (eg. 80um)

Please review those values from the design rules that your fabricator specifies.

What could go wrong?

If such rules are violated in your designs, it can mean that SM might not properly manufacture which can impact quality of your soldering process during assembly. For example, if a "bridge" is too small, small slivers of solder resist can detach and in worst case stay on top of a solder pad surface. This pad then cannot be soldered properly anymore.

Now let us see what else can happen due to the solder mask misalignment against the copper image. Why is there a misalignment between copper image and solder mask at all? Recall, that PCBs get fabricated on larger "fabrication panels", eg. 500mm x 500mm filled up with your "assembly panels" which themselves carry one or more of your single PCB.

Now recall how the multi-layer PCB is treated until it is covered with solder resist. During putting the "cores" and "laminates" together, they are treated with eg. 15 bar of pressure. Do you think, the conductive pattern which you designed in your PCB tool is exactly at the coordinates that you specified – of course not. Ask your fabricator about this parameter, but assume on a distance of 10cm, maybe you have a position accuracy of +/- 10um. Now think on the panel level, it could mean your "conductive pattern" are dispositioned by maybe 50um from the origin - on panel level.

The solder mask might be manufactured by photo plot using a film. The film itself has a different expansion coefficient compared to the PCB, so that is why there might be a misalignment between your “conductive pattern” and your "solder mask pattern" and obviously this misalignment is not the same for the various "assembly panels".

I did a small animation about such misalignment between copper and solder mask. The copper is in red, the solder mask opening is green and "gold" for areas where we have a solder mask opening on top of copper (means areas of unprotected copper). The solder mask oversize is 75um. I am showing a disposition of SM against conductive pattern by 75um in possibly any direction. Check your fabricators specification for "Conductive pattern to solder resist", possibly you will see values of 50-100um. To keep the animation short, I just showed a misalignment in few directions. As you see, the solder mask opening on top of a trace right next to a solder pad. What do you think might happen during soldering? Solder bridges between pad and trace might be the result, which costs the effort and time of repair. But maybe, the assembly plant analyzes this failure and because they cannot change the PCB design data anymore, maybe they do some "tuning" on the solder paste definition.

Of cause there are many more design rules which PCB fabricator specifies to us, like all kinds of minimum object to object clearances. A PCB Designer should learn what is the reason for such design rules. If you understand the reason, driven by manufacturability and why the rule exist, then you will understand why the PCB fabricator has an interest that you follow the rule or even worse, why the CAM operator at the fabricator might change your GERBER data in a way, that he can run smoothly thru his production to optimize his profit!

I am sorry to tell you this, PCB fabricators do sometimes change the GERBER data in a way, that it even can change the electrical performance of your product. Of cause, you can bind them by contract to tell you about all the changes they recommend to do and why they are needed. At least you should compare the "manipulated" manufacturing data against the data that you had sent.

The bad thing with all this is. Maybe you have two different fabricators A and B for prototypes and series production and the CAM operators at A and B make recommend and apply different changes. I am just reporting to what my clients told me has happened to them. A prototype supplier under time pressure might just take decissions.

A few examples of what changes are possibly made.

  • Maybe you had too thin traces in your design. CAM operator might widen them.
  • Maybe you violated minimum sizes of annular rings. CAM operator might enlarge them.
  • Maybe you have slivers in the conductive pattern, CAM operator might change the drawing.
  • and many more other reasons

Just for purpose of demonstration, I configured my PCB Editor in a bad way, as if I had just done a mistake. I have "flooded" my copper planes using lines of 1 mil (~25um) width and I defined such a pad-to-plane clearance, that two very small bridges can result in copper as shown in the next picture. You will see a lot more critical items in the picture but I just highligthed the bridges. What you are seeing in the following image is a thru-hole connector P1, it's five pins and copper flooded around them.

The CAM operator might not allow this to go into manufacturing. For example for this reason. The conductive pattern is checked by an AOI (Automated Optical Inspection). Because the "bridge" is so small, sometimes it will be there, sometimes it will not be there after manufacturing. This means, AOI will give warning many times. In order to prevent this -because this costs money-, CAM operator will change the GERBER data so AOI can run smooth. In this case possibly by removing this "bridge" from the GERBER data. Now imagine we had a Thru-hole connector row with many of those small "bridges" which got removed. Such change could result in a "slot" structure as shown in the next picture.

Think further, if there were high-speed relevant signals in adjacent layer. Maybe such changes to the GERBER data would have broken the HF-return path of the signal. So manufacturing wise, all looks good, but we changed the electrical performance.

Clearly, we have to take care. We shall not have structures in our PCB fabrication data that forces the PCB fabricator to make changes to those data!

What could a PCB-Design engineer do about it?

Check what kind of DFF-rules your PCB-Editor does allow. I am familiar with "Xpedition" and "PADS Professional" from Mentor, a SIEMENS business [2] and show some screenshots how this software can enter and visualize such rules and violations. The DFF checks from "PADS Professional", there are hundreds. You need to set the correct parameters as specified by your fabricator. Then you might save those for later reuse as a "DFF scheme" for each of your fabricators like "Fab A STD" as shown in the next picture or maybe some common scheme that fits for most of your fabricators.


If you have a good DFF tool, it will show you sample pictures of the type of check. If you are uncertain as to why a rule exists, well, ask your PCB fabricator, he can tell you the manufacturing reason behind.

If your PCB-Editor of choice does not allow for such DFF checks, then screen the market for such tools. THere are quite some tools on the market who can operate with Gerber or preferably ODB++/IPC2581 input. Also feel free to contact with me for consultancy.


We shall not have structures in our PCB fabrication data that forces the PCB fabricator to make changes to those data!

(of course I mean changes other than for photo transfer reasons)

As we want all our manufacturing to run smooth. That is why you might want to analyze your PCB-Layout using DFF-Design rules. You notice, we ask the PCB designer to take care about an issue that will increase or lower the profit of someone else. But at the end, it will be the profit of the company that you work for. Someone in your company must have an interesst to consider DFF/DFM methodology.

It might be that your PCB-Design tool is able to do DFF. It might be that you want to run additional software tools on your manufacturing data. No matter how you do it – do it!


[1] www.multi-circuit-boards.eu, public data about Basic Design Rules for PCB

[2] www.pads.com/professional, Manual on DFF rules[/vc_column_text][/vc_column][/vc_row]

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