Don’t forget the Via- and Pin-Length when trace-length matching

Don’t forget the Via- and Pin-Length when trace-length matching

In diesem Artikel auf Englisch erklärt Hans Hartmann, Sales Manager DACH von Cadlog GmbH, einige wichtige Aspekte beim Trace-Length Matching. Still many PCB-Layout editors in the market do not support the length thru a Via connection when matching a group of signals for same length (or for same timing, which by far many PCB-Editors can't do at all). I must say, this also is not necessary for all designs. But as your signals are getting faster and your requirements for length/time matching getting tigther, you should not overlook this detail.

For my article, I like to use the PCB Layout data of the "Beagle Bone Black" design. It is a design of an ARM-based micro-controller along with DDR3 memory. The design data is available on the web-site (*1). I have imported that design into my PCB-Tool and demonstrate a couple of things related to length matching about the DDR3 address lines.

I make some simplifications to the design rules, just for the purpose of this article. So I am just giving a design constraint that all DDR3 address lines shall have the same length within a tolerance of 250um (~10 mils) between longest and shortest. In a correct setup, I would have setup Address, Command, Clock requirements. Such a constraint could be setup in a constraint manager tool, filling the table. The picture shows a "Constraint Class" which got called "DDR3_ADR", to which I had assigned all address lines and then given the rule to match within 0.25mm. I could have setup alternatively to match a required time tolerance.

I want to analyze the routing of the DDR3 bus bundle. The general routing overview is shown here.

With this wrong setup, the interactive DRC (Design Rule Check) indicates that there is no violation in length matching, so all traces from longest to shortest do match within 0.25mm and all is marked as "Tuned". Those 0.25mm were possibly the original intent for this design done in another tool.

This actual trace-length information from layout can also be brought back into the "Constraints Manager" so that a design-engineer working on the schematic, but not having a PCB-Editor could also review it. So what we are seeing is that DDR_A15 is the longest track and the shortest one is DDR_A4 being 0.222mm shorter.

Again, I prepared for demonstration purpose, the PCB-Editor in a way that it behaves as many other PCB-Editor. But now, let us do it more precise.

The routing of the address lines was done using Inner and Outer layers. So Top, Bottom, Layer 3 and Layer 5 got used in a mix. I am showing here only a 3D view of A0 and A1 address lines. A0 used Top, Layer-5, Layer-3 routing. A1 used Top and Layer-3 routes. Hence both signals take a significantly different length thru the involved via connections. A0 use one via more and in two via, the signal travels almost the hole via-length. Remember, the board thickness is about 1.6mm.

Again, I prepared for demonstration purpose, the PCB-Editor in a way that it behaves as many other PCB-Editor. But now, let us do it more precise.

Now I setup the PCB-Editor to take care for via-length calculation and consideration. And -no surprise- now a different net is the longest one and we do not meet anymore our length-matching requirements! We miss it in one case by ~2.7mm! So we detect that the design could still get some improvement to add tuning meander, which in the tool that I am using could be done automatically.

This information can also be loaded into the "Constraints Manager".

There is also another and different view to this topic. The reason for length-matching is, because we want all signals to have about the same arrival time in respect to a clock-signal. So essentially, what we are asking is that all address lines have the same "flight time" (or TOF = Time Of Flight). But this requirement of TOF-matching is often turned into a length-matching requirement, even though I had explained in this article (Inner vs Outer Layer Routing), that eg. 1cm of routing on Top-Layer is very different in timing versus 1cm on Layer-3. You could have done this, if you had decided to route all address lines on a single eg. inner layer (except for the fanout, which has to be on Top).

[added Rev.2]

After the first version of this article, Antoon send a comment to not forget about "pin package length/delay". So let us talk about it too. An IC is some semiconductor die inside a package. Obviously there is a connection between the contact pad on the die and the solder pad of the package. Think about a "bond wire" but the connection can be very different depending on the package construction. This connection has a characteristic that can be expressed as a "length" or as a "flight time" which shall be considered when routing traces on the PCB. Here is how a PCB-Editor (if it supports that sort of rules) can catch such values in the "Constraints Manager".

The 6300-0002 is the part number of the Microprocessor that was used. We are seeing all the BGA package pins.

DDR_A0 is connected to BGA ball "F3". In the moment of writting this article, unfortunately I couldn't access the information about package internal length for this Microprocessor. So just as an example, I am specifying 1.3mm.

In general, you might get from the component manufacturer this information as a length or a delay for each pin. Indeed, depending on the product and the package size, it might be that chip internal length can be "large". In the past I have seen 16mm. I went to the web-site of an FPGA manufacturer to review some values. I saw values even upto in the range of 200ps (~3cm trace length equivalent) - indeed significant values, as Antoon had commented. Watch out if your IC specifies very different internal length/delay for the pins on a bus-interface .

Following picture is again the interactive DRC and timing check. The tools calculates us all the contributors for "length" or "flight time", i.e. the traces, the Via and the chip internal length. In this case shown, DDR_A0 is now reported at length 28.10903, which is the specified 1.3mm longer than before. Now we can get active and make the tuning in consideration of all relevant parameters.


If you are routing high-speed critical signals, consider what your PCB-Editor is truly able to do for you. I am experienced with "PADS Professional" and made the screenshots with that tool.

As you can see for this choosen example. This is a working product and hardware is quite tolerant. But if you drive your DDRx memory interfaces towards their bandwidth limits, you must consider the concepts explained here and possibly use a Signal-Integrity analysis tool to consider even more relevant effects for signal-quality and -timing (i.e. "Signal Integrity") that a PCB-Layout editor can not take care of. Examples would be Crosstalk or stub-length in a Via and it's relevance to disturb Signal Integrity.



(2) Screenshots taken from "PADS Professional/Xpedition" software from Mentor, a SIEMENS business,

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