How to verify “Current Carrying Capacity” in a PCB Design
In diesem Artikel auf Englisch erklärt Hans Hartmann, Sales Manager DACH von Cadlog GmbH, wie die "aktuelle Tragfähigkeit" in einem PCB-Design überprüft werden kann.
In this article I want to talk about current carrying capacity in PCB (Printed Circuit Boards). Why it is "difficult" to accurately predict without simulation. How we can use charts to give practical recommendations such as IPC-2152 (and formerly IPC-2221) in order to avoid simulation. Then I will show how a PCB-Layout engineer can validate his design easily by means of an easy to use simulation tool.
"Can my trace of 5mm width carry sufficient current?"
Say we have a PCB of 160mm x 100mm x 1.6mm thickness. On this PCB, we have a trace on layer top and copper thickness is 35um (~1 oz).[/vc_column_text][vc_single_image image="37600" size="full" overlay="none" item_link_type="no-link"][vc_column_text]What is the answer to the following question?
"I have a 5 mm wide trace, how much current can it carry?"
The clear answer is, "well, it depends". Do you want to know when the trace reaches a temperature and starts to catch fire? Ok, the answer depends on some more details to be asked. So let me ask the question this way.
"How much current can a 5 mm wide trace carry, when it shall heat up by no more than about 40°C"
I am afraid to say, the answer is still, "well, it depends". In a simulation tool capable of simulating all details of electrical current flow in solid bodies as well as all mechanism of heat transfer, I made some simplified setup to show what will happen to our trace. Let us do the assumption, that we have the above specified PCB and this 5mm wide trace on an outer layer at 35um copper thickness. In the following animation, I am showing simulation results for: 1A to 9A of current that passes thru that trace and I show the surface temperature above the trace on the PCB. Let me explain later about simulation setup and assumptions that I made.[/vc_column_text][vc_single_image image="37610" size="full" overlay="none" item_link_type="no-link"][vc_column_text]Observation: We might get the impression, that we can pass 9A thru the trace and the temperature on the surface over the trace will nowhere heat up by more than <50°C above ambient (ambient @ 35°C in this case) and most of board area stays near ambient temperature. Let me explain basics about heat transfer and then do changes to our board and see what we will observe then.
The current flow thru the trace will result in electrical power P = I*I*R dissipated in the trace i.e. electrical current thru electrical resistance of the trace, electrical resistance even being temperature dependent. The electrical power is equivalent to "heat". There are different mechanisms how this heat can "travel" and leave our board from the point where it is produced to the "colder ambient". If the heat would not leave at all, our PCB would get very hot and catch fire. Hopefully, the heat will leave the board towards the ambient and therefore will get to a temperature higher than the ambient, but still sufficiently low. Depending how easy the heat can leave the PCB, will determine how much hotter our board will be compared to ambient.
How can "heat" leave our PCB?
- Heat can exchange by "Convection" i.e. on surfaces between solids and fluids, where our fluid is often just the "air" surrounding our PCB
- Heat can exchange thru "Radiation" between surfaces of different temperatures by radiation in the IR spectrum
- Heat can exchange thru "Conduction" in solids, eg. thru constructions elements into the housing and from there to the ambient
For simplification of the before mentioned simulation, I modelled that heat cannot leave by means of radiation (which is not true in reality!). I further modelled for simplification, that the surface of the PCB can exchange heat with the environment, say at 5W/sqmK (this tells us: on a surface of one square-meter, for every 5 Watts exchanged thru the surface, our surface gets one Kelvin hotter than the ambient). Of cause such equal heat-exchange factor on every point on our surfaces is not valid in reality but is valid for simplifying my further illustration. In reality, our PCB is surrounded often by a fluid eg. "air". The heat exchange on the surface depends how this fluid can take heat away from the surface. Which itself depends on parameters like amount of air-flow, the temperature of the fluid, the turbulence, gravitation, humidity and several more. If you want to make a more accurate analysis, you need to use a simulation tool that can calculate "Convection" as well, besides flow of electrical current in the electrical conductors. Some "CFD" software on the market can do this.
In any case, the heat must travel from where it is generated, to the surface of the PCB (to be more accurate, surfaces including all surfaces of electrical components on the board or surface enlarging elements such as heat-sinks). It depends on the actual PCB-Layout (mix and distribution of copper and dielectrics) of the PCB, how heat can travel inside the PCB towards the surface. It depends on the environment of our PCB (the "ambient") how easy heat can leave from the surface.
Do you think that was already the final answer, a 5mm wide trace can carry 9A and heats up by no more than 50°C? Of course not…
Now let me make a change to the PCB. In an inner layer, I will create a copper-plane, same size as the board itself, fully flooded. This obviously impacts the thermal conductivity of the board and hence impacts how heat can travel from the trace to the whole surface. Copper has about a 1000x better thermal conductivity than FR4. Which means, a power-plane inside a board acts like a heat spreader. In the following picture you will see the simulation results. As you see, indeed, heat seems to travel more easy towards the whole surface from where is gets transferred away. The PCB stays cooler.
Observation: The same amount of current (9A) leads now to only ~11°C temperature raise above ambient.
Now let me show that what happens when we change the assumption of heat-exchange to say 3W/sqmK.
Observation: The same amount of current (9A) leads to ~14°C temperature raise above ambient.
Now let us change the copper plane inside the PCB and make it only flooded left half-side of the PCB. Again doing this, we do massively influence the thermal conductivity of the bare board. As you see, the PCB gets a very different temperature distribution on the surface. The heat can leave more easily from the left half side of the trace because on the left side we have the heat-spreading support of the copper plane in the left half-side.
Observation: The same amount of current (9A) leads now to 19°C and to 38°C temperature raise above ambient at the two shown observation points.
Just as a reference, in the next image, I am showing the inner layer temperature of the copper plane.
Conclusion: I have shown, that you cannot safely answer the question, how much current a trace can carry and how much the temperature will raise. Because it depends on many parameters, that you would need to use a simulation tool, capable of taking care of all those parameters and physical effects, to accurately predict what will happen. Such tools exist, that is not the problem.
However we cannot ask PCB Designers to make those time intensive simulations all the times.
What else can a PCB-Layout Engineer do?
For example in IPC2221 and much for actual in IPC2152 are charts, which show for traces the relationship between current passing thru a trace with a certain cross section area and how the trace will heat up. I do not dare to copy here any chart of the IPC-2221 for copyright reason, but try to get access to those. The charts look like this…Essentially it gives the PCB-Layouter a guideline to know about what cross-section area of traces have to be constructed if a certain electrical current has to be carried and a certain max. temperature raise will be allowed.
Later on for IPC2152, much more parameters got taken into account and there is more information available to give guidance for a PCB-Layout engineer.
The values that I read from those charts (IPC 2221, traces on outer layer), I translated into other values like "max. allowed current densisty" and the other values shown in the table.
Let us apply those values now for a small example circuitry. Transistors charging an inductance. See the two small current paths T1 -> L1 and L1 -> T2 and possible implementation in the PCB-Layout.
If both paths shall carry 10A @ max. 10°C temperature raise on a layer with 70um thickness of copper, then we require a minimum trace width of 3.8mm (149mil) which cannot be routed by a trace, because as of clearance rules against the shown obstacles. See in the following image an implementation by wide traces, but one segment can meet only up to 3.1mm instead of 3.8mm because of clearance rules.
So we decide for an implementation using plane-shape-routed style using one layer. This then requires, that we are using measurement tool in the PCB-Editor, visually try to identify the path that the DC current will take and measure if we always meet the required width ie. cross-section area. You hopefully agree, this can be painful and easy to make a mistake.
Now let us assume, the requirement for minimum cross-section could not be achieved by routing on one layer and we needed even a second layer. For creating a meaningful example, I used a second routing layer but constructed a different shape on the second layer.
Again, it is error prone task, to validate now on two routing layer if the width (cross-section) is meeting the requirements.
How could we do that in another way?
Remember our IPC tables. Our requirement 10A / 10°C at given 70um copper thickness, could also be translated into a requirement to have nowhere more than: 37.8 A/sq.mm (24.4mA/sq.mil)
Now let me show you how to do this with a simulation tool, that gives us the current density, anywhere in the copper, no matter if routing was done by shapes, by traces, no matter what the copper thickness was. All is taken care. For the purpose of this article, I was using "PADS HyperLynx DC Drop", a simulation addon to the "PADS" PCB-Design Software from Mentor a SIEMENS Business. By the way, this exists also in other configurations for users of all other types of PCB-Design tools, as long as they can export ODB++ or IPC2581.
Being in "HyperLynx", I made two simulation runs. Nominating T1/T2/L1 as Voltage sources or Current sinks. Just as simple as modelling the Transistor pin as a 200V Voltage source and the Inductor pin as a 10A current-sink. This takes me very little (minutes) of setup time. Then I do simulations which run in a few ten seconds and give me results in form of reports and moreover very nice graphical pictures for documentation. For example a visualization of current-density as vector plot.
Current-Density Visualization: 10A between T2/L1 in the implementation with shape-based routing on only one layer.
Current-Density Visualization: 10A between T1/L1 in the implementation with shape-based routing on two layer with different shapes.In those pictures you saw also an "inspection cursor". So you could easily inspect the current density in each point of the layout. There are also other possibilities to plot the result, but this would go beyond the scope of this article.
If you are using PCB-Layout Editor and HyperLynx DC Drop, both from Mentor, then you would be able to setup within the Constraint Manager of the PCB-Layout Editor, the requirement for max. current density and then have it validated by the simulation tool.Summary
I tried to illustrate that most accurate analysis of "current carrying capacity" of traces or shapes will depend on many parameters. The same trace (cross section area) will behave different from project to project depending of the rest what else is on the board and what the stackup is. I gave inspiration that software tools exist, which can make a very detailed and accurtate prediction of what can happen. I then proposed that such simulations in every project is maybe too much of work for a PCB-Designer. Instead, we might want to look into IPC 2221 better IPC2152 in order to get advise what trace width (cross section area) to construct depending on actual design-parameters in our project. I then proposed to conclude about "max. Current Density" and verify this max. current density by means of much more simple simulation tools. Only in case where you need to reach more of the possible limits, start to use simulations tools that can take care about much more relevant parameters to even more accurately analyse your PCB-Layout.
Call for action
If you have an actual project where you like to share your experience or are looking for support in verification, feel free to contact me.
Users Manual of software "HyperLynx Thermal"
Screenshots of software "HyperLynx DC Drop", "PADS Professional" Layout Editor and Constraints Manager and "FloTherm XT" CFD and Thermal Analysis software.[/vc_column_text][/vc_column][/vc_row]