Propagation Delay of Traces / Inner vs Outer Layer Routing

In diesem Artikel auf Englisch erklärt Hans Hartmann, Sales Manager DACH von Cadlog GmbH, wie Signal-Laufzeiten in Leiterbahnen / Routing auf Innen- versus Außen-Lagen funktionieren.

I like to talk about different trace propagation delays in inner-layers versus on outer-layers. Again, reason being, that a couple of our customers had asked me how to set the correct constraints in PCB Design tools for doing length matching or propagation-delay matching. The formula that is most commonly used to calculate propagation velocity of an electrical signal on a trace is:

On typical PCB material we get the rule of thumb values at Er=4, we have about ~15cm/ns or ~169ps/inch. Now let us look a bit more in detail into the two types of traces and geometry assumptions for which the above formulas are valid. Traces that are on an outer layer and in reference to only one Reference-Plane (eg. a Ground Plane). We call them a “Microstrip”. Traces that are on an inner layer in reference to two Reference-Planes above and below the trace. We call those a “Stripline”. The next image shows what parameters determine the propagation delay (3 cm trace length).

With the parameters of that example, we see 207.5ps (and by the way an impedance of 50Ω). Notice also the electrical resistance (@20°C) and it’s inductance and capacitance.

The dielectric heights, dielectric constants and geometry of trace influence the traces R,L,C and hence Z0. (Z0 is frequency dependent. The value shown is based on the loss-less formula for higher frequencies.

The propagation delay depends “only” on the dielectric constant. See for example the second image in which I am showing and changed dielectric heights. Propagation delay is same 207.5ps, only R,C,L and Z0 changed.

Now notice in the next image, how another change in dielectric heights will not change the propagation delay but will change R,L,C,Z0.

Now let us see what parameters will influence a “Microstrip” on a outer layer. Because the “effective” Er (Epsilon-R) around the trace is important and because the trace is on an outer layer, we need a model, that is modelling the effect of a solder mask covering. See the next image. I made a stackup construction and choose a trace-width, so that we get again a 50Ω impedance for comparison.[

A 3cm of trace-length would get 181ps of delay.

Observation: A 3cm microstrip and a 3cm stripline can get a very different propagation delay!

Conclusion: If we would route a bundle of traces, eg. a bundle of DQ/DQS data and strobe lines of a DDRx memory interface. If we length-match them, we still need to take care that length need to match on the same layer! So we can for example length-match them provided we have exact same length on outer layer (eg. same short length for fanout into Via).

But on outer layer, it is even more tricky. See the next image where I changed the thickness of the Soldermask.

Observation: It is impacting our Z0 but also our propagation delay in a significant way, at least if we have high-speed and timing critical signals on the outer layer.

Why is that? Because the EM-field around the trace goes further than the soldermask thickness and hence reach the surrounding material. In the case of this model it is “air” which has an Er=1.

Conclusion: Timing critical signals on outer layers need to get extra care to control the dielectric around. That is we need to control the soldermask material and thickness as well as taking care when there is eg. special coating on the surface or the PCB is not surround by “air” but maybe by a molding material.

Can this article now finish? If I am asking like that, guess what, I like to raise your attention on one more topic.

Is propagation delay the "only" important thing that matters to meet signal timing requirements?

Of course not. Allow me to make comparison of two routing scenarios. See the next picture.

In both cases I made a setup in a signal integrity simulator, actually HyperLynx. The Setup is two IC-driver using IBIS simulation model of a 4Gb DDR3 memory, both times DQ0 pin, hence exact same simulation model will drive into a 50Ω load. The routing is on Layer-Top, thru a Via into Layer-3, thru a Via back onto Layer-Top.

Please check the details. This example is constructed in way

  • all trace segments are of same impedance, 50Ω
  • I implemented, by purpose, different lengths on inner- and outer-layer
  • the routed length is different, in order to match for the exact same “propagation delay”
  • both signals pass exact same way thru Vias

When we simulate this, we will expect that both signals arrive at exact same time at the load, right? The simulation result is in the next image and to our "surprise", we see some amount of skew, measured at an arbitrary voltage level of 0.8V. The skew is 2.78ps!

Observation: The two signals do not arrive at the same time, although we constructed the two different interconnects to have exact same propagation delay.

The explanation is simple. Our traces have indeed the exact same propagation delay but the interconnect have different R,L,C even though, by construction, the Z0 is the same. In the next picture we see the RLC of each segment.

Path-1: R=0.189Ω / C=4.6116pF / RC=0.87ps

Path-2: R=0.240Ω / C=4.6246pF / RC=1.11ps

So the signal in path-2 arrives a little bit later at the arbitrary measurement threshold of 0.8V.

Conclusion: Even if you matched the timing of your signals, which is by far better than only length-matching, still then you have differences. The differences might be in the range of few pico-seconds. However, that might already be a relevant difference in a fast DDRx memory interface.

Now I make even another scenario to demonstrate you something. We simulate the same interconnect again, but this time with the IBIS models of the DQ0 and DQ1 of the same device.

Observation: The skew is now 3.49ps (DQ0/DQ1 models) compared to 2.78ps (both DQ0 models)

Explanation: The chip internal delay varies from pin to pin. In IBIS models, the package delay is often modeled by an RLC values.

[Pin]         signal_name model_name  R_pin       L_pin       C_pin

B3            DQ0        DQ          290.49m     1.31nH      0.45pF

C7            DQ1        DQ          264.40m     1.24nH      0.42pF

Which gives us even further details that could be obeyed. For example you might get values for package internal length or package internal delay that you can enter in your PCB design tools as design rules.


In this article I explained how propagation delays are calculated. You can use a variety of tools, even free spreadsheet calculation tools. I showed the calculations how they are made with HyperLynx software. Then I suggested to take care when you consider if “length matching” is what you want to do versus “matching of propagation delays”.

In case you are doing really high-speed designs and want to length match within a few pico-seconds tolerance, then you should use software tools that really do a simulation. HyperLynx with its "DDRx-Wizard" is such a tool. It does not only validate automatically all timing, but looks also onto all waveforms of all involved signals and verifies them against many more rules that exist on DDRx signals.

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